الفهرس الالي لمكتبة كلية العلوم و علوم التكنولوجيا

Titre :	High-performance D/A-converters : application to digital transceivers
Type de document :	texte imprimé
Auteurs :	Martin Clara ; SpringerLink (Service en ligne
Editeur :	Heidelberg : Springer-Verlag
Année de publication :	2013
Importance :	1 texte électronique
Présentation :	fichiers PDF
Format :	24 *17cm
ISBN/ISSN/EAN :	978-3-642-31229-8
Note générale :	In SpringerLink Titre de l'écran-titre (visionné le 12 mars 2013)
Langues :	Français (fre)
Mots-clés :	High  performance D/A  converters  PERFORMANCE FIGURE OF D/A CONVERTERS  DYNAMIC LINCARDY NOISESSHAPED D/A CONVERTERS  ADVANCED CURRENT CALIBRATION  CONCLUSION AND CALIBRATIONJ  CONCLUSION AND OUTLOOK  DAC BIAS MODEL  JITTER NOISE
Index. décimale :	621.3
Résumé :	In SpringerLink Titre de l'écran-titre (visionné le 12 mars 2013) This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.
Note de contenu :	This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.

High-performance D/A-converters : application to digital transceivers [texte imprimé] / Martin Clara ; SpringerLink (Service en ligne . - Heidelberg : Springer-Verlag, 2013 . - 1 texte électronique : fichiers PDF ; 24 *17cm.
ISBN : 978-3-642-31229-8
In SpringerLink Titre de l'écran-titre (visionné le 12 mars 2013)
Langues : Français (fre)

Mots-clés :	High  performance D/A  converters  PERFORMANCE FIGURE OF D/A CONVERTERS  DYNAMIC LINCARDY NOISESSHAPED D/A CONVERTERS  ADVANCED CURRENT CALIBRATION  CONCLUSION AND CALIBRATIONJ  CONCLUSION AND OUTLOOK  DAC BIAS MODEL  JITTER NOISE
Index. décimale :	621.3
Résumé :	In SpringerLink Titre de l'écran-titre (visionné le 12 mars 2013) This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.
Note de contenu :	This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.